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P re li mi na ry D ata S he et , DS 1, D ec em be r 20 01
T E 3 -L I U TM Line Interface Unit for D S 3 , S T S 1 a nd E 3
P EF 3 45 2 V e r s i on 1 . 3
W ir ed Co m mu n ic a ti o n s
Never stop thinking.
Edition 2001-12-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81669 Munchen, Germany
(c) Infineon Technologies AG 2001. All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
P re li mi na ry D ata S he et , DS 1, D ec em be r 20 01
P EF 3 45 2 V e r s i on 1 . 3
W ir ed Co m mu n ic a ti o n s
Never stop thinking.
P
R
E
LI
M
IN
Line Interface Unit for D S 3 , S T S 1 a nd E 3
A
R
T E 3 -L I U TM
Y
PEF 3452 PRELIMINARY Revision History: Previous Version: Page 24 27 28
2001-12-05
DS1
Preliminary Data Sheet TE3-LIU V1.2, 2001-07, DS3
Subjects (major changes since last revision) Chapter 4.1.4 Table 10 Figure 12
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com
PEF 3452 TE3-LIU V1.3
Table of Contents 1 1.1 1.2 1.3 2 2.1 2.2 3 3.1 3.2 3.3 3.3.1 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.5.1 4.1.5.2 4.1.5.3 4.1.6 4.1.6.1 4.1.6.2 4.1.6.3 4.1.7 4.1.8 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.6.1 4.2.6.2 4.2.6.3 4.2.7 4.3 4.4 Page 1 2 4 5
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Receiver Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Monitoring Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Line Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AMI Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B3ZS Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDB3 Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 LOS Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STS-1 LOS Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E3 LOS Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jitter Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intrinsic Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Line Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AMI Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B3ZS Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDB3 Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AIS Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Framer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maintenance Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 17 18 18 21 21 21 22 23 24 24 24 24 25 25 25 25 26 27 28 29 29 30 31 32 33 33 33 33 33 34 34 35
Preliminary Data Sheet
2001-12-05
PEF 3452 TE3-LIU V1.3
Table of Contents 4.4.1 4.4.2 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.7.1 6.4.7.2 6.4.7.3 6.5 6.6 6.7 7 8 8.1 8.2 Page
Remote Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Local Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Line Inactive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jitter Attenuator Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Template E3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Template DS3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Template STS-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 37 37 37 38 38 39 40 42 42 43 44 46 47 48 49 49 50 52 54 54 55
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Cable Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Preliminary Data Sheet
2001-12-05
PEF 3452 TE3-LIU V1.3
List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Page
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 T3/T1 Multiplexer Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Channelized T3 Link Layer Application . . . . . . . . . . . . . . . . . . . . . . . . . 5 Unchannelized T3 Link Layer Application . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Receiver Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DS3 Line Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Receive Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 E3 Loss of Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Jitter Tolerance Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Transmitter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Transmit Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Jitter Attenuation Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Remote Loop Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Local Loop Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Reference Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 XTAL Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Recommended Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Crystal Pulling Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Chip Select Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 XCLK Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 RCLK Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 E3 Pulse Shape at Transmitter Output . . . . . . . . . . . . . . . . . . . . . . . . 49 DS3 Pulse Shape at the Cross Connect Point (450 ft.) . . . . . . . . . . . . 50 STS-1 Pulse Shape at the Cross Connect Point (450 ft.) . . . . . . . . . . 52 Thermal Behavior of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Input/Output Waveforms for AC Testing . . . . . . . . . . . . . . . . . . . . . . . 55 DS3 Cable Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Preliminary Data Sheet
2001-12-05
PEF 3452 TE3-LIU V1.3
List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Page
Interface Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Control Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Hardware Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Hardware Indication Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 External Component Values for Receiver . . . . . . . . . . . . . . . . . . . . . . 21 External Component Values for DS Line Monitoring . . . . . . . . . . . . . . 22 E3 Receive Return Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Input Jitter Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 External Component Values for Transmitter . . . . . . . . . . . . . . . . . . . . 29 E3 Transmit Return Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Jitter Attenuation PLL Operation Frequencies . . . . . . . . . . . . . . . . . . . 31 Transmit Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Power Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Reset Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 REFCLK Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 XTAL Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 XTAL Crystal Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Chip Select Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . 46 XCLK Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 RCLK Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 E3 Pulse Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 DS3 Pulse Mask (ANSI T1.404, GR-499-CORE) . . . . . . . . . . . . . . . . 50 DS3 Pulse Mask (ANSI T1.404) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DS3 Pulse Mask (GR-499-CORE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 STS-1 Pulse Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 STS-1 Pulse Mask (ANSI T1.102) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Package Characteristic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Preliminary Data Sheet
2001-12-05
PEF 3452 TE3-LIU V1.3
PRELIMINARY
Preface
The PEF 3452 (TE3-LIUTM) is a flexible line interface unit for a wide area of telecommunication and data communication applications. The device is addressed to fulfill all requirements to build a DS3, STS-1 or E3 line interface.
Organization of this Document This Preliminary Data Sheet is organized as follows: * Overview Gives a general description of the product, lists the key features, and presents some typical applications. * Pin Descriptions Lists pin locations with associated signals, categorizes signals according to function, and describes signals. * Functional Description Describes the functional blocks and principle operation modes. * Interface Description Describes the device interfaces. * Operational Description Shows the operation modes and how their initialization. * Electrical Characteristics Specifies maximum ratings, DC and AC characteristics. * Package Outlines Shows the mechanical values of the device package. * Appendix * Index
Preliminary Data Sheet
2001-12-05
PEF 3452 TE3-LIU V1.3
PRELIMINARY Related Documentation This document refers to the following international standards (in alphabetical/numerical order): ACA TS016 (general requirements for Australia) CTR-24/TBR-24 (E3 requirements) ETS 300 166 (E3 transmit return loss) ITU-T G.703 (E3 pulse mask, B3ZS/HDB3 code, E3 receive return loss) ITU-T G.751 (jitter requirements E3) ITU-T G.775 (loss of signal definition) ITU-T G.823 (jitter requirements E3) ITU-T G.824 (jitter requirements DS3) ITU-T O.151 (pseudo random binary sequence (PRBS) definition) GR-253-CORE (STS-1 jitter requirements) GR-499-CORE (DS3 pulse mask, DS3 jitter requirements) ANSI T1.102 (STS-1 pulse mask) ANSI T1.102 Annex B (DS3 monitoring) ANSI T1.231 (maintenance functions, defect definitions) ANSI T1.404 (DS3 pulse mask) MIL-STD 883D (ESD requirements)
Your Comments We welcome your comments on this document. We are continuously trying improving our documentation. Please send your remarks and suggestions by e-mail to com.docu_comments@infineon.com Please provide in the subject of your e-mail: device name (TE3-LIUTM), device number (PEF 3452), device version (Version 1.3), and in the body of your e-mail: document type (Preliminary Data Sheet), issue date (2001-12-05) and document revision number (DS1).
Preliminary Data Sheet 2001-12-05
PEF 3452 TE3-LIU V1.3
PRELIMINARY Overview
1
Overview
The TE3-LIUTM PEF 3452 Line Interface Unit is used to connect a DS3/STS-1 or E3 framer device to an analog transmission line. The line interface fulfills the relevant standards for DS3 (44.736 Mbit/s), STS-1 (51.840 Mbit/s) and E3 (34.368 Mbit/s) systems. The TE3-LIUTM comes in a P-MQFP-44-2 package (SMD) to save a significant amount of board space. The integrated jitter attenuation further reduces overall system complexity and cost. This CMOS 3.3 V low power device contains an integrated pulse shaper to drive any line length within the range of up to 1100 ft. without the need for external length selection (Line Build Out). The hardware configuration mode allows low cost systems with flexible device setting without the need for a microprocessor. An optional microprocessor mode allows the connection to a standard microprocessor bus to control hardware settings.
Preliminary Data Sheet
1
2001-12-05
PRELIMINARY
Line Interface Unit for DS3, STS1 and E3 TE3-LIUTM
PEF 3452
Version 1.3
1.1
Features
* Generic analog interface for all DS3/STS-1/E3 applications * Single chip solution for receive and transmit direction * 3.3 V low power device * Integrated receive equalization network * Integrated noise and crosstalk filter * Clock and data recovery using an integrated PLL P-MQFP-44-2 with ultra-low intrinsic jitter * Transmit clock duty cycle correction PLL * No external components required for clock and data recovery and receive equalizer * DSX receive line monitor (additional 20 dB gain according to ANSI T1.102) * Low transmitter output impedances for high transmit return loss * Disable function of the analog transmit line outputs * Transmit pulse shaper to fulfill requirements of ANSI T1.404, Telcordia GR-499-CORE, ANSI T1.102 and ITU-T G.703 (E3) * Maximum line length up to 1100 ft. (using standard coaxial cable, for example AT&T 728A, 734A or 734D) * External line length selection (LBO) is not required * Jitter specifications of GR-499-CORE and ITU-T G.823 are met * Integrated jitter attenuation PLL and buffer in transmit direction * Dual or single rail digital inputs and outputs from/to the framer interface * Selectable line codes (HDB3 (E3), B3ZS (DS3/STS-1), AMI) * Analog and digital loss of signal detection and indication * Automatic RDOP/RDON blanking option in case of LOS * Bipolar violation indication * Local loop and remote loop for diagnostic purposes * Insertion of alarm indication signal ("all ones") * Flexible hardware or software controlled device configuration * Device power down function
Type PEF 3452 H V1.3
Preliminary Data Sheet 2
Package P-MQFP-44-2
2001-12-05
PEF 3452 TE3-LIU V1.3
PRELIMINARY Hardware Interface Mode * * * * * * * * * * * * * * * DS3/STS-1 or E3 Line Coding (E3: HDB3 or AMI; DS3/STS-1: B3ZS or AMI) Transmitter disable Power down Remote loop Local loop Single/dual rail operation Receive clock edge selection Transmit clock edge selection Transmit "all ones" Receive line monitoring mode Automatic RDOP/RDON blanking option Jitter attenuation Loss of signal indication Bipolar violation indication Overview
Microprocessor Interface Mode * Microprocessor bus compatible interface * Hardware control lines directly accessible General * * * * * * CMOS device P-MQFP-44-2 package (body size 10 mm x 10 mm, lead pitch 0.8 mm) Single power supply: 3.3 V 5% 5V-tolerant digital input lines Temperature range of -40C to +85C Low power device
Applications * * * * * * Interface for SONET/DS3 and E3 network equipment WAN gateways CSU/DSU Multiplexers Digital crossconnect systems DS3/STS-1/E3 Test Equipment
Preliminary Data Sheet
3
2001-12-05
PEF 3452 TE3-LIU V1.3
PRELIMINARY Overview
1.2
Logic Symbol
VDDRP VSSRP
VDDR VSSR
VDD VSS
REFCLK
TMS TCK TDI TRS TDO
RL1 RL2
RDOP RDON/BPV RCLK
XTAL1 XTAL2 XL1 XL2
PEF 3452 TE3-LIUTM
LOS
XDIP XDIN XCLK HW + P Access
DS3/STS-1 DS3/E3
VDDXP VSSXP
DR/SR XPE RPE MON RL LL LCODE XAIS XLT BLE CS
VDDX VSSX
RES
JATT
F0229
Figure 1
Logic Symbol
Preliminary Data Sheet
4
2001-12-05
PEF 3452 TE3-LIU V1.3
PRELIMINARY Overview
1.3
Typical Applications
Figure 2 to Figure 4 show typical applications using the TE3-LIUTM.
28 x DS1 digital DS3 digital
TE3_LIUTM TE3-MUXTM
QuadLIUTM #1
DS1 #1 analog
DS3 analog
QuadLIUTM #7
DS1 #28 analog
F0087
Figure 2
T3/T1 Multiplexer Application
DS3 analog
TE3-LIUTM
TE3CHATTTM
F0217
Figure 3
Channelized T3 Link Layer Application
DS3 analog
TE3-LIUTM
TE3-MUXTM
DSCC4
F0140
Figure 4
Unchannelized T3 Link Layer Application
5 2001-12-05
Preliminary Data Sheet
PEF 3452 TE3-LIU V1.3
PRELIMINARY Overview
Note: TE3-MUX TM (PEB 3445) is an M13 MUltipleXer/demultiplexer with an integrated DS3 framer QuadLIUTM (PEB 22504) is a 4-channel Line Interface Unit for E1/T1/J1 DSCC4TM (PEB 20534) is a 4-channel Serial Communication Controller TE3-CHATTTM (PEB 3456) is a CHAnnelized T3 Termination with DS3
Framer, M13 Multiplexer, T1/E1 Framers and 256 Channel HDLC/PPP controller
Preliminary Data Sheet
6
2001-12-05
PEF 3452 TE3-LIU V1.3
PRELIMINARY Pin Descriptions
2
2.1
Pin Descriptions
Pin Diagram
P-MQFP-44-2 (top view)
RDON/BPV
REFCLK
RDOP
RCLK
XCLK
XDIN
XDIP
VDD
RES
VSS
TRS TDI TMS VDDXP XTAL2 XTAL1 VSSXP TCK TDO JATT VDDX
33 34
31
29
27
25
CS
23 22
LOS XLT
36
20
RL LL
38
40
PEF 3452 TE3-LIUTM
18
VDDRP VSSRP
16
XAIS BLE
42
14
MON LCODE
44 1
3
5
7
9
12 11
DR/SR
VSSX
RPE
XPE
XL1
XL2
RL1
DS3/E3
VSSR
RL2
DS3/STS1
VDDR
F0230
Figure 5
Pin Configuration
7 2001-12-05
Preliminary Data Sheet
PEF 3452 TE3-LIU V1.3
PRELIMINARY Pin Descriptions
2.2
Table 1 Pin No.
Pin Definitions and Functions
Interface Pin Functions Symbol Input (I) Output (O) Supply (S) I (analog) Function
Receive Direction 9 RL1 Line Receiver 1 Analog input from the external transformer (receive bipolar ring). The signal at RL1 must be coded according to B3ZS or HDB3. Line Receiver 2 Analog input from the external transformer (receive bipolar tip). The signal at RL1 must be coded according to B3ZS or HDB3. Receive Data Output/Positive Received data at RL1/2 is sent on RDOP/ RDON to the framer interface. Data is clocked with the rising or falling edge of RCLK, depending on RPE. In single rail mode (DR/SR=0), data is sent in NRZ format. Receive Data Output/Negative If dual rail data format is selected, the negative data signal is output on RDON/ BPV. Bipolar Violation If single rail data format is selected, the bipolar violation indication signal is output on RDON/BPV. BPV is synchronized on RCLK. O Receive Clock Receive Clock extracted from the incoming data pulses. The active clock edge is determined by RPE. During LOS, a clock signal is generated internally and driven on RCLK (derived from REFCLK).
10
RL2
I (analog)
25
RDOP
O
24
RDON
O
BPV
26
RCLK
Preliminary Data Sheet
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PEF 3452 TE3-LIU V1.3
PRELIMINARY Table 1 Pin No. Interface Pin Functions (cont'd) Symbol Input (I) Output (O) Supply (S) O (analog) Function Pin Descriptions
Transmit Direction 1 XL1 Transmit Line 1 (transmit bipolar ring) Analog output to the external transformer. XL1 can be switched into inactive mode. Transmit Line 2 (transmit bipolar tip) Analog output to the external transformer. XL2 can be switched into inactive mode. Transmit Data In/Positive Transmit data received from the framer interface to be output on XL1/2. NRZ or dual rail positive data has to be provided at XDIP. Latching of data is done with the rising or falling transitions of XCLK, depending on XPE. Transmit Data In/Negative If dual rail format is selected, negative data signal is read from XDIN. If single rail data format is selected, data on XDIN is ignored. Latching of data is done with the rising or falling transitions of XCLK, depending on XPE. Transmit Clock Input of the working clock for the transmitter. The active clock edge is determined by XPE. DS3: 44.736 MHz STS-1: 51.840 MHz E3: 34.368 MHz To fulfill e.g. ITU-T G.832 a clock accuracy of 20 ppm is required. For correct function a clock signal has always to be supplied to XCLK.
3
XL2
O (analog)
31
XDIP
I + PU
32
XDIN
I + PU
30
XCLK
I + PU
Preliminary Data Sheet
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PEF 3452 TE3-LIU V1.3
PRELIMINARY Table 1 Pin No. Interface Pin Functions (cont'd) Symbol Input (I) Output (O) Supply (S) I Function Pin Descriptions
Global Clock Reference 29 REFCLK Reference Clock REFCLK is the basic internal clock. It must be stable during reset and operation. This clock is also used to synchronize the receive PLL in case of no signal. The clock frequency depends on the target application: DS3: 44.736 MHz STS-1: 51.840 MHz E3: 34.368 MHz To fulfill e.g., ITU-T G.832 a clock accuracy of 20 ppm is required. 39 38 XTAL1 XTAL2 I O Jitter Attenuation Reference Connection for an external pullable crystal. DS3: 14.912 MHz STS-1: 17.280 MHz E3: 11.456 MHz If jitter attenuation is disabled (default), XTAL1 is internally driven to a fixed level (not floating).
Preliminary Data Sheet
10
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PEF 3452 TE3-LIU V1.3
PRELIMINARY Table 2 Pin No. Control Pin Functions Symbol Input (I) Output (O) Supply (S) I Function Pin Descriptions
33
RES
Hardware Reset A low signal at this pin forces the device into reset state. Chip Select 0 = hardware control signals are switched through 1 = hardware control signals are ignored DS3/STS-1 or E3 Select Primary mode selection. This signal has to be stable during reset and may not change afterwards. It must not be connected to a P bus. 0 = E3 1 = DS3 or STS-1 (see DS3/STS-1) DS3 or STS-1 Select Primary mode selection. This signal has to be stable during reset and may not change afterwards. It must not be connected to a P bus. 0 = STS-1 1 = DS3 Line Code Select for receive and transmit direction E3: 0 = AMI 1 = HDB3 DS3/STS-1: 0 = AMI 1 = B3ZS
23
CS
I + PU
5
DS3/E3
I + PU
4
DS3/STS-1
I + PU
13
LCODE
I + PU
16
XAIS
I + PU
Transmit Alarm Indication 0 = no AIS 1 = AIS all-ones insertion
Preliminary Data Sheet
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PEF 3452 TE3-LIU V1.3
PRELIMINARY Table 2 Pin No. Control Pin Functions (cont'd) Symbol Input (I) Output (O) Supply (S) I + PU Function Pin Descriptions
20
RL
Remote Loop Switching 0 = no loop 1 = Remote Loop 1) Local Loop Switching 0 = no loop 1 = Local Loop1) Transmitter inactive 0 = transmitter enabled 1 = transmitter disabled (outputs 1.5 V common mode voltage) Line Monitoring Mode 0 = additional 20 dB gain at RL1/RL2 1 = normal Blanking Enable 0 = detected signal is switched through even in case of LOS 1 = all-zero signal is sent on RDOP/RDON in case of LOS, REFCLK is used to drive RCLK Dual Rail/Single Rail Select The framer interface is operated either in dual rail or single rail mode. In single rail mode, the BPV signal is output on RDON/ BPV and input on XDIN is ignored. 0 = single rail 1 = dual rail RCLK Positive Edge Selection 0 = RDOP, RDON are clocked with negative (falling) edge of RCLK 1 = RDOP, RDON are clocked with positive (rising) edge of RCLK XCLK Positive Edge Selection 0 = XDIP, XDIN are clocked with negative (falling) edge of XCLK 1 = XDIP, XDIN are clocked with positive (rising) edge of XCLK
12 2001-12-05
19
LL
I + PU
21
XLT
I + PU
14
MON
I + PU
15
BLE
I + PU
12
DR/SR
I + PU
6
RPE
I + PU
7
XPE
I + PU
Preliminary Data Sheet
PEF 3452 TE3-LIU V1.3
PRELIMINARY Table 2 Pin No. Control Pin Functions (cont'd) Symbol Input (I) Output (O) Supply (S) I + PD Function Pin Descriptions
43
JATT
Jitter Attenuation Enable This signal has to be stable during reset and may not change afterwards. It must not be connected to a P bus. 0 = no jitter attenuation (default if left open) 1 = jitter attenuation in transmit direction Loss of Signal Indication 0 = correct signal 1 = loss of signal LOS is synchronized on RCLK. During LOS, a clock signal is generated internally and driven on RCLK.
22
LOS
O
1)
If RL=LL=1, the device is set into power down mode.
Preliminary Data Sheet
13
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PEF 3452 TE3-LIU V1.3
PRELIMINARY Table 3 Pin No. Power Supply Pins Symbol Input (I) Output (O) Supply (S) S (analog) S (analog) S (analog) S (analog) S (analog) S (analog) S (analog) S (analog) S Function Pin Descriptions
11 8 44 2 18 17 37 40 27
VDDR VSSR VDDX VSSX VDDRP VSSRP VDDXP VSSXP VDD
Positive Power Supply for the analog receiver Power Supply Ground for the analog receiver Positive Power Supply for the analog transmitter Power Supply Ground for the analog transmitter Positive Power Supply for the analog receiver PLL Power Supply Ground for the analog receiver PLL Positive Power Supply for the analog transmitter PLL Power Supply Ground for the analog transmitter PLL Positive Power Supply for digital subcircuits and the digital receiver output Power Supply Ground for digital subcircuits and the digital receiver output
28
VSS
S
Preliminary Data Sheet
14
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PEF 3452 TE3-LIU V1.3
PRELIMINARY Table 4 Pin No. Test Pins 1) Symbol Input (I) Output (O) Supply (S) I + PU Function Pin Descriptions
34
TRS
TAP Controller Reset Active low test controller reset; this pin must be connected to RST or VSS Test Data Input Test Mode Select Test Clock Test Data Output
35 36 41 42
1)
TDI TMS TCK TDO
I + PU I + PU I + PU O
These pins are used for factory test only; boundary scan mode is not provided.
Note: PU = input or input/output comprising an internal pullup device PD = input or input/output comprising an internal pulldown device To override the internal pullup (pulldown) by an external pulldown (pullup), a resistor value of 47 k is recommended. Unused pins containing pullups or pulldowns can be left open.
Preliminary Data Sheet
15
2001-12-05
PEF 3452 TE3-LIU V1.3
PRELIMINARY Functional Description
3
3.1
Functional Description
Functional Overview
The TE3-LIUTM device contains analog and digital functional blocks, which are configured and controlled by direct hardware or microprocessor control. The main interfaces are * * * * Receive Line Interface Transmit Line Interface Framer Interface Hardware Interface
The main internal functional blocks are * Analog line receiver with noise & crosstalk filter, equalizer network and clock/data recovery * Analog line driver with programmable pulse shaper * Central clock generation module * Jitter attenuator * Maintenance functions (e.g., loop switching local or remote) * Hardware/microprocessor control interface
Preliminary Data Sheet
16
2001-12-05
Preliminary Data Sheet 17 2001-12-05
Figure 6 Block Diagram
RL1 RL2 20 dB Gain Stage Noise Filter MON Local Loop LL XL1 XL2 Line Driver & LBO XLT Hardware/P Interface XAIS LCODE XPE RPE XLT MON LL RL DR/SR BLE CS LOS
3.2
PRELIMINARY
Autom. Gain Control
Level Detection
ALOS Detection LOS, BLE LOS Detection LOS
Block Diagram
Var. Gain Amplifier
Equalizer
Clock & Data Recovery
Decoder
RCLK RDOP RDON/BPV
REFCLK
DR/SR LCODE DS3/STS1/E3 Remote Loop RL
Transmit PLL
Jitter Attenuator PLL
XTAL1 XTAL2 JATT
Pulse Shaper
Jitter Attenuator Buffer
AIS Insertion
Encoder
XCLK XDIP XDIN
XAIS Mode Control General Control Test Mode Control
DR/SR LCODE DS3/STS1/E3
Functional Description
PEF 3452 TE3-LIU V1.3
JATT
DS3/STS-1
DS3/E3
REFCLK
RES
TDO
TDI
TMS
TCK
TRS
F0231
PEF 3452 TE3-LIU V1.3
PRELIMINARY Functional Description
3.3 3.3.1
Functional Blocks Hardware Control Unit
All hardware control signals except DS3/E3, DS3/STS-1 and JATT are gated by CS. All other control signals are gated by CS to allow an easy connection to a microprocessor (P) data bus. DS3/E3, DS3/STS-1 and JATT may not be connected to a data bus. If direct hardware control without P is intended, CS has to be connected to V SS. After reset all control input values are cleared. The default control values (driven by internal pullups) are activated after CS = low is applied for the first time after reset. Table 5 Hardware Control Functions Control Signal DS3/E3 0 = E3 1 = DS3 or STS-12) DS3/STS-1 0 = STS-1 1 = DS32) This pin is ignored, if E3 mode is selected by DS3/E3 = 0 DR/SR 0 = single rail data on RDOP and XDIP 1 = dual rail data on RDOP/RDON and XDIP/XDIN2) RPE 0 = data change on negative edge 1 = data change on positive edge2) XPE 0 = data change on negative edge 1 = data change on positive edge2) LCODE 0 = AMI 1 = HDB3 (E3)2) 1 = B3ZS (DS3/STS-1)2)
Device Function Selection of E3 or DS3/STS-1 mode1)
Selection of DS3 or STS-1 mode1)
Dual rail select
Receive clock edge selection
Transmit clock edge selection
Selection of line coding
Send AIS (all-ones alarm indication signal) XAIS 0 = no insertion 1 = AIS insertion2)
Preliminary Data Sheet
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PEF 3452 TE3-LIU V1.3
PRELIMINARY Table 5 Hardware Control Functions (cont'd) Control Signal RL 0 = normal operation 1 = remote loop LL 0 = normal operation 1 = local loop LL 00 01 10 11 & RL = normal operation = remote loop operation = local loop operation = power down2) Functional Description
Device Function Select remote loop
Select local loop
Select power down mode
Blanking enable
BLE 0 = data signal is switched through even in case of LOS 1 = all-zero signal is transmitted on RDOP/RDON in case of LOS using RCLK derived from REFCLK2) MON 0 = additional 20 dB gain stage activated 1 = normal amplifier setting2) XLT 0 = normal operation 1 = inactive2)3)4) JATT 0 = jitter attenuation disabled2) 1 = jitter attenuation enabled
Line monitoring mode
Transmitter inactive mode
Jitter attenuation enable
1) 2) 3) 4)
to be selected while reset is active (RST = 0) default, if pin is left open and CS has been asserted at least once outputs 1.5 V common mode voltage connecting of CS to VSS or asserting CS in parallel to RES suppresses spurious output on XL1/2
Preliminary Data Sheet
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PEF 3452 TE3-LIU V1.3
PRELIMINARY Table 6 Hardware Indication Signals Indication Signal LOS 0 = normal signal 1 = loss of signal BPV 0 = no violation 1 = bipolar violation Available in single rail mode only on pin RDON/BPV. Functional Description
Device Function Indicate LOS (loss of signal)
Indicate BPV (bipolar violation)
Preliminary Data Sheet
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PEF 3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4
4.1 4.1.1
Interface Description
Receiver Standard Receiver Application
75
1:1 RL1 C1 R1
TE3-LIUTM
RL2
F0080
Figure 7 Table 7 Parameter
Receiver Configuration External Component Values for Receiver Characteristic Line Impedance [] DS3 STS-1 75 75 100 1:1 E3
R1 ( 1 %) [] C1 ( 20 %) [nF] t2 : t1
The external components are the same for DS3, STS-1 and E3 applications.
Preliminary Data Sheet
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PEF 3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.1.2
Line Monitoring Application
DSX cross connect point
75
75
1:1 RL1 C1 R1
TE3-LIUTM
Receiver Mode RL2 MON=1
R3 1:1 RL1 C1 R2
TE3-LIUTM
Monitor Mode RL2 MON=0 F0081
Figure 8 Table 8 Parameter
DS3 Line Monitoring External Component Values for DS Line Monitoring Values 75 47 470 100 1:1
R1 ( 1 %) [] R2 ( 1 %) [] R3 ( 1 %) [] C1 ( 20 %) [nF] t2 : t1
The external components are according to ANSI T1.102 Annex B. The dimensions given above lead to a signal level at the monitor device input of approximately -20 dB below the level at the receiver device. Similar configurations using the line monitoring mode are possible in STS-1 or E3 applications.
Preliminary Data Sheet
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PEF 3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.1.3
Receive Line Interface
The receive line interface consists of a pre-amplifier, a noise and crosstalk filter, a variable gain amplifier and an equalizer followed by the clock and data recovery. The noise and crosstalk filter reduces distortions within the incoming analog signal. The VGA amplifies the analog signal and the equalizer compensates the frequency dependent line attenuation. Digital signal levels are formed within the retiming block of the clock and data recovery. Receive return loss requirements of ITU-T G.703 are fulfilled as required for E3 operation. Table 9 E3 Receive Return Loss Frequency Range from [kHz] 860 1720 34368 to [kHz] 1720 34368 51550 Return Loss [dB] 12 18 14
The equalizer contains an additional 20 dB gain stage, which is used in line monitoring mode to amplify resistively attenuated signals.
Reference Clock
Automatic Gain Control
Level Detection
False Lock Detection
RL1 RL2
20 dB Gain Stage
Noise & Crosstalk Filter
Variable Gain Amplifier
Equalizer
Receive PLL
Receive Clock
MON
Retiming
Dual Rail Receive Data
F0094 V1.3
Figure 9
Receive Clock System
Preliminary Data Sheet
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PEF 3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.1.4
Receive Clock and Data Recovery
The receive clock and data recovery extracts the route clock RCLK from the digital data stream and converts the data stream into a dual rail bit stream. The clock and data recovery needs a reference clock to keep the PLL stable during times without data signal at RL1/RL2. The clock that is output on pin RCLK is the recovered clock of the signal provided on RL1/RL2 and has a duty cycle close to 50 %. The intrinsic jitter generated in the absence of any input jitter is defined in Chapter 4.1.8. The PLL reference clock is generated internally without the need for external components.
4.1.5
Receive Line Coding
In E3 applications the HDB3 and the AMI coding is provided for the data received from the ternary interface. In DS3/STS-1 mode the B3ZS and AMI code is supported. In B3ZS or AMI code all code violations are detected and indicated.
4.1.5.1
AMI Code
The AMI code is defined as a dual rail data signal, where the combinations 00 ("0"), 10 ("+1") and 01 ("-1") are valid. No subsequent "+1" or "-1" bits are allowed, these will be detected as bipolar violations and indicated on pin RDON/BPV, if single rail mode is selected (according to ANSI T1.231 chapter 7.1). The received AMI data stream is either switched transparently to the framer interface as dual rail data or converted into a single rail data stream.
4.1.5.2
B3ZS Code
In the B3ZS line code each block of three consecutive zeros is replaced by either of two replacements codes which are B0V and 00V, where B represents a pulse which applies to the bipolar rule ("+1" or "-1") and V represents a bipolar violation (two consecutive "+1" or "-1" bits). The replacement code is chosen in a way that there is an odd number of valid B pulses between consecutive V pulses to avoid the introduction of a DC component into the analog signal. The receive line decoder decodes the incoming B3ZS data signal and changes the replacement patterns to the original three-zeros pattern. Pattern sequences violation these rules are reported as bipolar violation errors. Data output to the framer interface can be selected to be either dual rail or single rail.
Preliminary Data Sheet
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PEF 3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.1.5.3
HDB3 Code
In the HDB3 line code each block of four consecutive zeros is replaced by either of two replacements codes which are B00V and 000V, where B represents a pulse which applies to the bipolar rule ("+1" or "-1") and V represents a bipolar violation (two consecutive "+1" or "-1" bits). The replacement code is chosen in a way that there is an odd number of valid B pulses between consecutive V pulses to avoid the introduction of a DC component into the analog signal. The receive line decoder decodes the incoming HDB3 data signal and changes the replacement patterns to the original three-zeros pattern. Pattern sequences violation these rules are reported as bipolar violation errors. Data output to the framer interface can be selected to be either dual rail or single rail.
4.1.6
Alarm Handling
The receive line interface includes the alarm detection for loss of signal (LOS). LOS is indicated either if an analog or a digital loss of signal condition is detected. During LOS a clock signal is sent on RCLK. The clock is internally derived from REFCLK.
4.1.6.1
DS3 LOS Definition
Detection and recovery of digital LOS defects in DS3 mode is done according to ANSI T1.231: An LOS defect occurs when 175 contiguous pulse positions with no pulses of either positive or negative polarity at the line interface are detected. An LOS defect is terminated upon detecting an average pulse density of at least 33% over a period of 175 contiguous pulse positions following the receipt of a pulse. An LOS defect shall not be terminated if, at the end of the pulse-position interval, any subintervals of 100 pulse positions contain no pulses of either polarity.
4.1.6.2
STS-1 LOS Definition
Detection and recovery of digital LOS defects in STS-1 mode is defined in ANSI T1.231 (chapter 8.1.2.1.1) as follows: An LOS defect occurs upon detection of no transitions on the incoming signal (before descrambling) for time T, where 2.3 T 100 s. The LOS defect is terminated after a time period equal to the greater of 125 s or 2.5xT' containing no transition-free interval of length T', where 2.3 T' 100 s.
Preliminary Data Sheet
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PEF 3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.1.6.3
E3 LOS Definition
Analog LOS is detected, if the signal level on pins RL1/2 drops below a fixed level ("B") for a certain period. Loss of signal level "B" is defined to be between 15 and 35 dB below normal signal level "A". If the signal exceeds 35 dB for 175 contiguous pulse periods, analog LOS defect is indicated. Analog LOS defect is cleared, if the signal exceeds a threshold of 15 dB below nominal level for 175 contiguous pulse periods (10 N 255). See ITU-T G.775 for reference.
A
B
see ITU-T G.775 page 4
0 dB
Maximum cable loss
Nominal value
Level below Nominal
3 dB
15 dB
"transition condition" must be detected
Tolerance range, "no transition condition" or "transition condition" may be declared
35 dB
"no transition condition" must be detected
F0101 V1.2
Figure 10
E3 Loss of Signal Definition
Preliminary Data Sheet
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2001-12-05
PEF 3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.1.7
Jitter Tolerance
The TE3-LIUTM receiver's tolerance to input jitter complies to and exceeds the relevant international standards. Especially the requirements of Telcordia GR-499-CORE (DS3), ITU-T G.824 (DS3), GR-253-CORE (STS-1) and ITU-T G.823 (E3) are fulfilled and exceeded. Figure 11 and Table 10 show the different input jitter specifications. Low frequency jitter is called "wander", where the defined border between jitter and wander is 10 Hz for DS3/E3 and 100 Hz for STS-1.
Input Jitter Amplitude
A1 pass A2 fail
A3
F1
F2
F3 Jitter Frequency
F4
F5
F6
F0085
Figure 11 Table 10 Reference
Jitter Tolerance Principle Input Jitter Requirements A1 5 10 15 1.5 A2 [UIPP] 0.1 0.3 1.5 0.15 A3
not def. not def.
F1 10 10 10 100
not def.
F2 2300 669 30 1000 1.2 x 10-5
F3 60 x 103 22.3 x 103 300 10 x 103 10
F4 [Hz]
F5
F6
not def. not def. not def. not def.
GR-499-CORE, Category I GR-499-CORE, Category II GR-253-CORE, Category II ITU-T G.823 & ETSI TBR24 ITU-T G.824
300 x not def. 103 300 x not def. 103 2x 103 20 x 103
0.15
not def.
800 x not def. 103 600 30 x 103
18 s 5
0.1
400 x 103
Preliminary Data Sheet
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PEF 3452 TE3-LIU V1.3
PRELIMINARY Interface Description
100
10
Jitter Amplitude [UI]
pass area
1
fail area
0,1
0,01 0,10
1,00
10,00
100,00
1000,00
10000,00
100000,00
1000000,00
Jitter Frequency [Hz] GR-499-CORE Cat. 1 GR-499-CORE Cat. 2 ITU-T G.823 ITU-T G.824 GR-253-CORE Cat. 2 TE3-LIU TE3-LIU PUCCINI F0104 F0104
Figure 12
Jitter Tolerance
GR-499-CORE Jitter Tolerance Requirements (DS3) The input jitter tolerance is defined as the minimum amplitude of sinusodial jitter at a given frequency that when modulating the signal at an equipment input port results in more than 2 errored seconds in a 30-second measurement interval. Requirements on input jitter tolerances are then given in terms of a jitter tolerance mask, which represents the minimum acceptable jitter tolerances for a specified range of jitter frequencies. There are two different jitter tolerance masks defined for Category I (SONET interfaces) and Category II (non-SONET interfaces) equipment. GR-253-CORE Jitter Tolerance Requirements (STS-1) For Category I interfaces, the same requirements are used as defined in GR-499-CORE. For Category II interfaces that are specified as having reduced jitter tolerance, shall tolerate, as a minimum, input jitter applied according to the mask given in Table 10.
4.1.8
Receive Output Jitter
The intrinsic jitter of the receiver output signal RDOP/RDON/RCLK (if no input jitter is applied) is * E3: * DS3: * STS-1: < 0.06 UI < 0.08 UI < 0.10 UI
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PRELIMINARY Interface Description
4.2
Transmitter
The serial bit stream is then processed by the transmitter which has the following functions: * generation of AMI, B3ZS (DS3/STS-1) or HDB3 (E3) coded signals * all-ones generation (alarm indication signal)
4.2.1
Transmit Line Interface
The received data stream on pins XDIP (single rail data) or XDIP/XDIN (dual rail data) is converted into a ternary signal which is output on pins XL1 and XL2. In E3 mode the HDB3 and AMI line code are supported, in DS3/STS-1 mode the B3ZS and AMI is supported.
t1 : t2
R1 XL1
75
CP R1
TE3-LIUTM
XL2
F0079
Figure 13
Transmitter Configuration
Table 11 Parameter
External Component Values for Transmitter Characteristic Line Impedance [] DS3 STS-1 75 37.51) 372) 1:1 E3
R1 ( 1 %) []
Cp [pF]
t2 : t1
1)
This value refers to an ideal transformer without any parasitics. Any transformer resistance or other parasitic resistances have to be taken into account when calculating the final value for the output serial resistors. This value includes all parasitic capacitances on the secondary side of the transformer.
2)
The external components are the same for DS3, STS-1 and E3 applications. Transmit return loss requirements for E3 defined in ETS 300 166 are fulfilled. Pulse mask
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PRELIMINARY Interface Description
requirements according to ANSI T1.102 (at cross connect point, up to 450 ft.) are fulfilled.
Note: An additional capacitor on the primary or secondary side of the transformer may be required in some applications to improve the pulse mask, if the parasitic capacitances of the PCB are very small.
Table 12
E3 Transmit Return Loss Frequency Range Return Loss 1) to [kHz] 1720 51550
15
from [kHz] 860 1720
1)
[dB] 6 8
measured with an unframed PRBS 2 -1 pattern
4.2.2
Transmit Clock System
The supplied transmit clock XCLK is duty-cycle corrected by an internal PLL circuit to provide a 50% clock signal to the internal line driver unit. The pulse shaper working frequency is fourfold of the XCLK frequency. If the transmit clock XCLK is failing, an all-zero signal is generated automatically. If AIS insertion is selected, the output signal is referenced to REFCLK.
XAIS
fnom REFCLK JATT XTAL1 XTAL2 disable testmode fnom fnom : 3 Transmit PLL
Jitter Attenuator PLL XAIS fnom
fnom x 4
XCLK XDIP XDIN
Encoder
AIS Insertion
Jitter Attenuator Buffer
Pulse Shaper
Line Driver
XL1 XL2
F0232
Figure 14
Transmit Clock System
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Preliminary Data Sheet
PEF 3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.2.3
Jitter Attenuation
Jitter is reduced in transmit direction, if the jitter attenuator is activated (JATT = 1). The JATT control signal enables/disables the jitter attenuation PLL and activates/bypasses the buffer. The jitter attenuator consists of a buffer and a PLL. The jitter attenuation PLL delivers a "jitter free" clock (nominal frequency divided by 3, see Table 13) to the transmit PLL which generates the buffer read clock. The jitter attenuation PLL uses a pullable crystal and supports a tuning range of 150 ppm. The jitter attenuator uses a 64-bit dual rail buffer and fulfills the requirements of GR-499CORE and GR-253-CORE as shown in Figure 15. This covers the requirements of ITUT G.751, G.752 and G.755 as well. To avoid the need for a high frequency crystal, the reference clock for the jitter attenuation PLL is only one third of the nominal frequency. A detailed block diagram of the transmit clocking is given in Figure 14. Table 13 Jitter Attenuation PLL Operation Frequencies Jitter Attenuation PLL Input Frequency 44.736 MHz 51.840 MHz 34.368 MHz Jitter Attenuation PLL Output Frequency 14.912 MHz 17.280 MHz 11.456 MHz Crystal Frequency
Operation mode
DS3 STS-1 E3
14.912 MHz 17.280 MHz 11.456 MHz
Further requirements for the external crystal are found in Table 21 on page 45.
Preliminary Data Sheet
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PRELIMINARY Interface Description
20 dB/decade
0.5 dB 0.1 dB Jitter Gain
ITU-T G.755 & GR-499-CORE ITU-T G.751
- 20 dB TE3-LIU - 40 dB
ITU-T G.752 GR-253-CORE
10
40
100 300
1000
Jitter Frequency
10000 100000 15000
F0141
Figure 15
Jitter Attenuation Characteristic
4.2.4
Intrinsic Jitter
The TE3-LIUTM transmit PLL generates an output jitter which fulfills the requirements as specified in Table 14 below. Table 14 Specification GR-499-CORE (DS3) ANSI T1.404 (DS3) GR-253-CORE (STS-1) ETSI TBR24 (E3)
1)
Transmit Output Jitter Measurement Filter Bandwidth Lower Cutoff 10 Hz 10 Hz 30 kHz 12 kHz 100 Hz 10 kHz Upper Cutoff 300 kHz 400 kHz 400 kHz 400 kHz 800 kHz 800 kHz < 1.0 UIPP < 0.3 UIrms < 0.5 UIPP < 0.05 UIPP < 1.0 UIPP < 0.3 UIrms < 0.4 UIPP < 0.15 UIPP Output Jitter1)
Measured with maximum input jitter applied (see Figure 12).
Preliminary Data Sheet
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PRELIMINARY Interface Description
4.2.5
Pulse Shaper
The internal pulse shaper generates the required pulse shapes for E3, DS3 and STS-1 signals according to ANSI T1.102, T1.404, Telcordia GR-499-CORE and ITU-T G.703). The specific pulse mask is fulfilled at the crossconnect point at a distance of 0 to 450 ft. to the transmitter (DS3 requirement). The maximum line length between a TE3-LIUTM transmitter and TE3-LIUTM receiver is 1100 ft. for a coaxial cable of AT&T type 728A, 734A or 734D.
4.2.6 4.2.6.1
Transmit Line Coding AMI Code
The AMI code is defined as a dual rail data signal, where the combinations 00 ("0"), 10 ("+1") and 01 ("-1") are valid. Additionally no subsequent "+1" or "-1" bits are allowed (bipolar violations). A dual rail data stream is passed transparently, even if it contains bipolar violations. A single rail data stream is encoded to a correct AMI coded bipolar data stream without zero code suppression.
4.2.6.2
B3ZS Code
In the B3ZS line code each block of three consecutive zeros is replaced by either of two replacements codes which are B0V and 00V, where B represents a pulse which applies to the bipolar rule ("+1" or "-1") and V represents a bipolar violation (two consecutive "+1" or "-1" bits). The replacement code is chosen in a way that there is an odd number of valid B pulses between consecutive V pulses to avoid the introduction of a DC component into the analog signal. The transmit line encoder detects three-zeros pattern sequences and changes them to the appropriate replacement pattern. Although B3ZS coding is normally used with single rail NRZ data, the transmit line encoder accepts either dual rail or single rail data. Bipolar violations in an incoming dual rail data stream are converted to valid data pulses.
4.2.6.3
HDB3 Code
In the HDB3 line code each block of four consecutive zeros is replaced by either of two replacements codes which are B00V and 000V, where B represents a pulse which applies to the bipolar rule ("+1" or "-1") and V represents a bipolar violation (two consecutive "+1" or "-1" bits). The replacement code is chosen in a way that there is an odd number of valid B pulses between consecutive V pulses to avoid the introduction of a DC component into the analog signal. The transmit line encoder detects three-zeros pattern sequences and changes them to the appropriate replacement pattern.
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PRELIMINARY Interface Description
Although HDB3 coding is normally used with single rail NRZ data, the transmit line encoder accepts either dual rail or single rail data. Bipolar violations in an incoming dual rail data stream are converted to valid data pulses.
4.2.7
AIS Insertion
An unframed all-ones signal can be inserted into the transmitted data stream. To fulfill the required accuracy, a reference clock of 20 ppm is needed on pin REFCLK. If local loop configuration and AIS insertion is selected together, the AIS signal is looped back to RDOP/RDON.
4.3
Framer Interface
The interface to the receive framer is realized by RDOP, RDON and RCLK. Data at RDOP/N are clocked off with either the rising (RPE=1) or falling edge (RPE=0) of RCLK. Alternatively a single rail signal can be selected to be output on pin RDOP (DR/SR=0). Bipolar violation indications are output on pin RDON/BPV in this case. Data from the framer interface are sampled at XDIP and XDIN on the active edge of the XCLK. The active edge can be the rising (XPE=1) or falling edge (XPE=0) of XCLK. Alternatively a single rail signal can be used on pin XDIP (DR/SR=0).
Note: Selection of dual rail/single rail mode is common to receive and transmit direction.
See Figure 24 on page 47 and Figure 25 on page 48 for details.
Preliminary Data Sheet
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PRELIMINARY Interface Description
4.4 4.4.1
Maintenance Functions Remote Loop
In the remote loopback mode the clock and data recovered from the line inputs RL1/2 are routed back to the line outputs XL1/2. As in normal mode they are also processed by the synchronizer and then sent to the framer interface. Data passes the decoder and encoder circuit. The recovered receive clock is used to drive the transmit pulse shaper.
RL1 RL2
Noise & Crosstalk Filter
Equalizer
Clock & Data Recovery
Decoder
RDON RDOP RCLK
Remote Loop
XL1 XL2
Line Driver
Pulse Shaper
Jitter Attenuator
Encoder
XDIN XDIP XCLK
F0083
Figure 16
Remote Loop Signal Flow
Note: If remote loop and local loop are selected simultaneously, the device will be set into power down mode. Note: The jitter attenuator can be switched off optionally.
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PRELIMINARY Interface Description
4.4.2
Local Loop
The local loopback mode disconnects the receive lines RL1/2 from the receiver. Instead of the signals coming from the line data provided by system interface is routed through the analog receiver back to the framer interface. The transmit bit stream is sent to the transmit line unchanged. If XAIS=1 is selected, the transmit data stream is replaced by an all-ones signal and looped back.
RL1 RL2
Noise & Crosstalk Filter
Equalizer
Clock & Data Recovery
Decoder
RDON RDOP RCLK
Local Loop
XL1 XL2
Line Driver
Pulse Shaper
Jitter Attenuator
Encoder
XDIN XDIP XCLK
F0084
Figure 17
Local Loop Signal Flow
Note: If remote loop and local loop are selected simultaneously, the device will be set into power down mode. Note: The jitter attenuator can be switched off optionally.
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PRELIMINARY Operational Description
5
5.1
Operational Description
Operational Overview
The TE3-LIUTM can be operated in three principle modes, which are either E3, DS3 or STS-1 mode. This basic operation mode selection has to be stable before the reset signal goes inactive. The device is programmable by pin selection. Direct connection to a microprocessor data bus is possible by using the chip select pin (CS) as a write strobe.
5.2
Device Reset
The TE3-LIUTM is forced to the reset state if a low signal is input on pin RES (for minimum period see page 42). During reset, all output stages are in a high impedance state, all internal flip-flops are reset. The basic device mode (DS3, STS-1 or E3, jitter attenuation) has to be selected during reset to enable the internal PLLs to adjust. After reset all control input values are cleared. The default control values (driven by internal pullups) are activated after CS = low is applied for the first time after reset.
5.3
Device Power Down
The TE3-LIUTM can be set into power down state to reduce power consumption, if not active. Power down mode is selected by setting RL=LL=1. Receive and transmit circuits are switched off including internal PLLs and transmit line driver. Recovery from power down mode is achieved by clearing either of RL or LL (RL = 0 and/or LL = 0). After recovery from power down, the internal PLLs need to stabilize again. REFCLK must be active to recover from power down mode. Internal pullup resistors are not switched off during power down to prevent open input lines from floating.
Note: If switching directly from local loop to remote loop or vice versa, make sure that there is no signal overlap, which would set the device into power down mode unintentionally.
5.4
Transmit Line Inactive
If the transmitter is not used, it can be switched into inactive mode by setting XLT=1. During inactive state the common mode voltage of 1.5 V is output on XL1 and XL2. The transmit PLL is not stopped and output can be enabled again by XLT=0 without wait time.
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PRELIMINARY Electrical Characteristics
6
6.1
Table 15 Parameter
Electrical Characteristics
Absolute Maximum Ratings
Maximum Ratings Symbol Limit Values - 40 to 85 - 65 to 150 - 0.4 to 4.5 - 0.4 to 4.5 - 0.4 to 4.5 - 0.4 to 4.5 - 0.4 to 5.5 Unit C C V V V V V V
Ambient temperature under bias Storage temperature IC supply voltage (digital) IC supply voltage receive (analog) IC supply voltage transmit (analog) Voltage on any output pin with respect to ground Voltage on any input pin with respect to ground ESD robustness1) HBM: 1.5 k, 100 pF
1)
TA Tstg VDD VDDR VDDX VSO VSI
VESD,HBM 2000
According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993.
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
6.2
Table 16 Parameter
Operating Range
Power Supply Range Symbol Limit Values min. max. 85 3.46 C V 3.3 V 5% -40 3.13 Unit Condition
Ambient temperature Supply voltage
Digital input voltages Ground
TA VDD VDDR VDDX VDDRP VDDXP VID VSS VSSR VSSX VSSRP VSSXP
0 0
5.25 0
V V
5.0 V + 5%
Note: In the operating range, the functions given in the circuit description are fulfilled. All VDD pins have to be connected to the same voltage level, All VSS pins have to be connected to ground level. Note: Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and 3.3V supply voltage.
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
6.3
Table 17 Parameter
DC Characteristics
DC Parameters Symbol Limit Values min. max. 0.8 5.25 0.45 2.4 110 (typ.) V V V V mA - 0.4 2.0 Unit Notes
Input low voltage Input high voltage Output low voltage Output high voltage Average power supply current
VIL VIH VOL VOH IDD
IOL = + 4 mA1) IOH = - 4 mA 1)
typical (DS3, PRBS, JATT enabled, 3.3 V) worst case (STS-1, JATT enabled, AIS, 3.46 V)
155 (typ.)
Input leakage current Input leakage current Input pullup current Input pulldown current Transmitter leakage current
IIL11 IIL12 IIPU IIPU ITL
1 1 2 -2 25 5 (typ.) - 25 -5 (typ.) 1 1 200
A A A A mA mA A V V
VIN = VDD2) VIN = VSS2) VIN = VSS VIN = VDD
XL1/2 = VDDX, XLT = 1 XL1/2 = VSSX, XLT = 1 XL1/2 = 1.50 V3), XLT = 1 applies to XL1and XL24)
Transmitter output impedance
RX
5 (typ.) 2.0 VDDR+0. 3 tbd.
Differential peak voltage of VX a mark (at XL1/XL2) Receiver differential peak voltage of a mark (at RL1/RL2)
VR
RL1, RL2
Receiver input impedance ZR
k
3)
Preliminary Data Sheet
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PRELIMINARY Table 17 DC Parameters (cont'd) Symbol Limit Values min. Receiver sensitivity Analog loss of Signal threshold E3
1) 2)
Electrical Characteristics
Parameter (cont'd)
Unit Notes dB dB RL1, RL2
max. tbd. - 15
SRSH VLOS3
0 -35
applies to all output pins except analog pins XL1/XL2 Input leakage currents of pins containing internal pullup devices are measured in a testmode which switches off the pullups. test against common mode voltage, parameter not tested in production parameter not tested in production
3) 4)
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
6.4 6.4.1
AC Characteristics Reset
1 RES
2 DS3/E3 DS3/STS-1 JATT (PLLs tuned)
F0095
3
Figure 18 Table 18 No. 1 2 3
Reset Timing Reset Timing Parameter Values Limit Values min. max. s ns 1000 s 10 5 Unit
Parameter RES pulse width low DS3/E3, DS3/STS-1, JATT to RES setup time PLL startup time
Note: REFCLK must be active during reset.
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
6.4.2
Reference Clock
1 2 REFCLK 4 5
F0107
3
Figure 19 Table 19 No. 1
Reference Clock Timing REFCLK Timing Parameter Values Limit Values min. typ. 29.1 22.4 19.3 20 20 80 80 41) 41) 202) max. ns ns ns % % ns ns ppm Unit
Parameter REFCLK period E3 REFCLK period DS3 REFCLK period STS-1
2 3 4 5
1) 2)
REFCLK high REFCLK low REFCLK rise time REFCLK fall time Clock accuracy
not tested in production
if DS3-AIS function is not required, 200 ppm is sufficient to guarantee correct receive PLL function
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
6.4.3
Jitter Attenuator Reference Clock
1 2 XTAL1 4 5
F0164
3
Figure 20
*
XTAL Clock Timing XTAL Timing Parameter Values Limit Values min. typ. 87.29 67.06 57.87 max. ns ns ns Unit
Table 20 No. 1
Parameter XTAL1/2 period E3 XTAL1/2 period DS3 XTAL1/2 period STS-1
XTAL1
CL
TE3-LIUTM
XTAL2 CL
DS3: 14.912 MHz STS-1: 17.280 MHz E3: 11.456 MHz
F0245
Figure 21
Recommended Crystal Circuit
44 2001-12-05
Preliminary Data Sheet
PEF 3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
+200 +150 pulling range
F0259
f - f0 f0 [ppm]
+100 +50 0 -50 -100 -150 -200 10 15 20 nominal value
Load Capacitance CLeff [pF]
Figure 22 Table 21 No. 1
Crystal Pulling Range XTAL Crystal Parameter Values Limit Values min. typ. 14.912 17.280 11.456 25 7
1)
Parameter Crystal nominal frequency DS3 Crystal nominal frequency STS-1 Crystal nominal frequency E3
Unit MHz MHz MHz fF pF pF 30 pF
max.
2 3 4 5 6
1)
Crystal motional capacitance C1 Crystal shunt capacitance C0 Crystal load capacitance CLeff Crystal resonance resistance Rr Internal parasitic load capacitance CLint
15 7.5
This value includes the capacitance of the external capacitors (CLext) plus all internal (CLint) and external parasitic capacitances (CLpara). The value of the external capacitor has to be chosen depending on the printed circuit board layout. A typical value for CL is 0 to 10 pF, CL should be adapted to the parasitics to achieve a symmetrical pulling range.
Note: C Leff = C Lext + CLint + CLpara C Lext = 0.5 x CL
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
6.4.4
Microprocessor Control
1 CS 3 Control Signal 4
2
F0097
Figure 23 Table 22 No. 1
Chip Select Timing Chip Select Timing Parameter Values Limit Values min. max. ns ns ns ns ns ns ns ns 2.5 x TRCLK E1 DS3 STS-1 73 56 50 2.5 x TRCLK E1 DS3 STS-1 73 56 50 10 10 Unit
Parameter CS pulse width low
2
CS pulse width high
3 4
Control Signal Setup Time Control Signal Hold Time
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
6.4.5
Transmit Input Timing
1 2 XCLK (XPE=0) 6 XCLK (XPE=1) data change edge XDIP, XDIN
F0090
3
7
4
5
Figure 24 Table 23 No. 1
XCLK Input Timing XCLK Timing Parameter Values Limit Values min. typ. 29.1 22.4 19.3 30 30 2 2 11) 11) 202) 70 70 max. ns ns ns % % ns ns ns ns ppm Unit
Parameter XCLK period E3 XCLK period DS3 XCLK period STS-1
2 3 4 5 6 7 8
1) 2)
XCLK high XCLK low XDIP, XDIN setup time XDIP, XDIN hold time XDIP, XDIN, XCLK rise time XDIP, XDIN, XCLK fall time Clock accuracy
not tested in production
if DS3-AIS function is not required, 200 ppm is sufficient to guarantee correct PLL function
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
6.4.6
Receive Output Timing
1 2 RCLK (RPE=0) 5 RCLK (RPE=1) 4 RDOP, RDON data change edge
F0108
3
6
Figure 25 Table 24 No. 1
RCLK Output Timing RCLK Timing Parameter Values Limit Values min. typ. 29.11) 22.41) 19.31) 40 40 0 50 50 1 2 2 60 60 22) 52) 52) max. ns ns ns % % ns ns ns Unit
Parameter RCLK period E3 RCLK period DS3 RCLK period STS-1
2 3 4 5 6
1) 2)
RCLK high RCLK low RDOP, RDON delay time RDOP, RDON, RCLK rise time RDOP, RDON, RCLK fall time
not tested in production
applies only while the receiver PLL is locked to a valid signal on RL1/RL2, e.g., not in case of LOS
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
6.4.7 6.4.7.1
Pulse Templates Pulse Template E3
17 ns (14.55 + 2.45)
V
0.1
1.0
0.1
0.2
0.2
8.65 ns (14.55 - 5.90) Nominal pulse 14.55 ns
0.5
12.1 ns (14.55 - 2.45)
24.5 ns
0.1
(14.55 + 9.95)
0
0.1
0.2
29.1 ns (14.55 + 14.55)
T1818860-92
FIGURE 17/G.703
Pulse mask at the 34 368-kbit/s interface
0.1
F0076
Figure 26 Table 25 No.
E3 Pulse Shape at Transmitter Output E3 Pulse Mask1) Limit Values min. typ. 1.0 - 0.1 14.55 0.95 0.95 1.05 1.05 0.1 max. V V ns Unit
Parameter Nominal peak voltage of a mark (pulse) Peak voltage of a space (no pulse) Nominal pulse width Amplitude ratio of positive to negative pulses2) Pulse width ratio of positive to negative pulses3)
1)
measured at the output port without transmission line and 75 load; bit sequence: 0000000(+1)0000000(-1)0000000(+1)0000000(-1)... at the center of a pulse interval at the nominal half amplitude
2) 3)
Preliminary Data Sheet
49
0.1
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PRELIMINARY Electrical Characteristics
6.4.7.2
Pulse Template DS3
1.2
1.0
0.8 Normalized Amplitude
0.6 GR-499-CORE 0.4
0.2 ANSI T1.404 0
-0.2 -1.0 -0.5 0 Time [unit intervals] 0.5 1.0 1.5
F0077
Figure 27 Table 26
DS3 Pulse Shape at the Cross Connect Point (450 ft.) DS3 Pulse Mask (ANSI T1.404, GR-499-CORE)1) Absolute Voltage Level (100 % Value) min. 0.36 V max. 0.85 V
1)
bit sequence: 0000000(+1)0000000(-1)0000000(+1)0000000(-1)...
Preliminary Data Sheet
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PRELIMINARY Table 27 DS3 Pulse Mask (ANSI T1.404) Lower Curve Time T -0.36 -0.36 T +0.36 T +0.36 Equation -0.03
o o
Electrical Characteristics
T 0.5 1 + sin -- 1 + ---------2 0.18
e ae e ae
- 0.03
-0.03
Upper Curve Time T -0.68 -0.68 T +0.36 T +0.36 Equation +0.03
o o o o o o
T0.5 1 + sin -- 1 + ---------2 0.34
e ae e ae
+ 0.03
0.05 + 0.407 x e -1.84 [ T - 0.36 ]
Table 28
DS3 Pulse Mask (GR-499-CORE) Lower Curve Time -0.85 T -0.36 -0.36 T +0.36 +0.36 T +1.4 Upper Curve Time -0.85 T -0.68 -0.68 T +0.36 +0.36 T +1.4 Equation +0.03 T0.5 1 + sin -- 1 + ---------2 0.34 + 0.03 Equation -0.03 T 0.5 1 + sin -- 1 + ---------2 0.18 -0.03 - 0.03
0.08 + 0.407 x e -1.84 [ T - 0.36 ]
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
6.4.7.3
1.2
Pulse Template STS-1
1.0
0.8 Normalized Amplitude
0.6
0.4
0.2
0
-0.2 -1.0 -0.5 0 Time [unit intervals] 0.5 1.0 1.5
F0109
Figure 28 Table 29
STS-1 Pulse Shape at the Cross Connect Point (450 ft.) STS-1 Pulse Mask 1) Signal Power min. - 2.7 dBm max. + 4.7 dBm
1)
bit sequence: (+1)0(-1)0(+1)0(-1)...
Table 30
STS-1 Pulse Mask (ANSI T1.102) Lower Curve Time -0.85 T -0.38 -0.38 T +0.36 +0.36 T +1.4 Equation -0.03
o o
T 0.5 1 + sin -- 1 + ---------2 0.18
e ae
- 0.03
-0.03
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
Upper Curve Time -0.85 T -0.68 -0.68 T +0.26 +0.26 T +1.4 Equation +0.03
o o
T0.5 1 + sin -- 1 + ---------2 0.34
e ae
+ 0.03
0.1 + 0.61 x e -2.4 [ T - 0.26 ]
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
6.5
Table 31 Parameter Input
Capacitances
Pin Capacitances Symbol CIN COUT COUT 5 8 8 Limit Values min. capacitance1) capacitance1) max. 10 15 20 pF pF pF all except XL1, XL2 XL1, XL2 Unit Notes
Output capacitance1) Output
1)
not tested in production
6.6
Package Characteristics
F0051
Figure 29 Table 32 Parameter
Thermal Behavior of Package Package Characteristic Values Symbol RthJA RthJC Rj Limit Values min. typ. 63 15 125 max. K/W single layer PCB, 30%/11 m K/W metallization, 1W, no convection C Unit Notes
Thermal Resistance1) Junction to Ambient Thermal Resistance2) Junction to Case Junction Temperature
1)
RthJA = (T junction - Tambient)/Power not tested in production RthJC = (Tjunction - Tcase)/Power not tested in production
2)
Preliminary Data Sheet
54
2001-12-05
PEF 3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
6.7
Test Configuration
AC Test Level
External Load
Device under Test Timing Test Points
VT
CL
Drive Levels
VIH VIL
F0206
Figure 30 Table 33 Parameter
Input/Output Waveforms for AC Testing AC Test Conditions Symbol CL1 CL2 CL3 VIH VIL VT RL TR TF Test Values 50 15 50 2.4 0.4 VDD/2 75 5% 10 - 90 90 - 10 Unit Notes pF pF pF V V V % % digital outputs except RDOP, RDON, RCLK digital outputs RDOP, RDON and RCLK analog line output XL1, XL2 all except RL1, RL2 all except RL1, RL2 all except XL1, XL2 XL1, XL2 not tested in production
Load Capacitance 1 Load Capacitance 2 Load Capacitance 3 Input Voltage high Input Voltage low Test Voltage Output Test Load Rise Times Fall Times
Note: Typical characteristics are mean values expected over the production spread. If not specified otherwise, typical characteristics apply at TA = 25 C and VDD = 3.3V. Note: Capacitance values include all parasitics caused by board layout, transformer etc.
Preliminary Data Sheet
55
2001-12-05
PEF 3452 TE3-LIU V1.3
PRELIMINARY Package Outlines
7
Package Outlines
P-MQFP-44-2 (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device
Dimensions in mm
Preliminary Data Sheet
56
2001-12-05
GPM05622
PEF 3452 TE3-LIU V1.3
PRELIMINARY Appendix
8
8.1
Appendix
Cable Characteristics
Cable characteristics are defined in ANSI T1.102 as shown below.
Office Cable Loss (450 ft. coaxial)
14
12
10 Insertion Loss [dB]
8
6
4
2
0 1 10 Frequency [MHz] 100
Office Cable Insertion Phase (450 ft. coaxial)
90
80
70
Insertion Phase [deg]
60
50
40
30
20
10
0 1 10 Frequency [MHz] 100
F0105 V1.1
Figure 31
DS3 Cable Characteristics
Preliminary Data Sheet
57
2001-12-05
PEF 3452 TE3-LIU V1.3
PRELIMINARY Appendix
8.2
Application Example
The following picture shows a typical application circuit (excluding surge protection).
Jitter Attenuation Reference
CL
CL
XTAL1/2 VDDRP/VSSRP
VDDR/VSSR
DS3/STS-1/E3 Receive Line Interface
RL1/2
Receive Path
RDOP RDON RCLK LOS
DS3/STS-1/E3 Framer/Mapper Receive Interface
TE3-LIUTM V1.3
DS3/STS-1/E3 Transmit Line Interface XDIP XDIN XCLK DS3/STS-1/E3 Framer/Mapper Transmit Interface
XL1/2
Transmit Path
VDDXP/VSSXP
VDDX/VSSX VDD/VSS REFCLK TEST
Reference Clock
N.C. Control Interface
F0233
Figure 32
Application Circuit
Preliminary Data Sheet
58
2001-12-05
PEF 3452 TE3-LIU V1.3
PRELIMINARY
Index A
AIS 11 Ambient temperature AMI 24 ANSI 10, 57 Applications 3, 5 38
Loss of Signal
13
M
MIL-Std 883D 38
O
Operating Range Output Jitter 28 39
B
B3ZS buffer 24 31
P
Package 54, 56 PLL 42 P-MQFP-44-2 56 Power Down 37 Power Supply 14, 38 Pulse Shaper 33 Pulse Template DS3 50 Pulse Template E3 49 Pulse Template STS-1 52
C
Cable 57 Clock 8, 10 Clock and Data Recovery crystal 31, 44 24
E
Edge Selection 12 ESD 38 External Component Values 21, 22
R
RCLK 48 Receive Clock 8 Receive Data 8 Receive Line Interface 8, 23 Receive Return Loss 23 Receiver 21 Reference Clock 10, 43 Remote Loop 12, 35 Reset 11, 37, 42, 46
H
HDB3 25
I
Input Jitter 27 international standards intrinsic jitter 24 ITU-T 10 10
S
Supply voltage 39
J
JATT 31 Jitter Attenuation 10, 13, 31, 32 Jitter Tolerance 27, 28
T
TAP Controller 15 Temperature 3 Thermal Behaviour 54 Transmit Clock 9 Transmit Data 9 Transmit Line 37 Transmit Line Interface 9, 29
L
Line Coding 11, 24 Line Monitoring 12, 22 Local Loop 12, 36
Preliminary Data Sheet
59
2001-12-05
PEF 3452 TE3-LIU V1.3
PRELIMINARY
W
wander 27
X
XCLK XTAL 47 44
Preliminary Data Sheet
60
2001-12-05
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Published by Infineon Technologies AG

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